Vertical NAND strings comprising a polysilicon channel may introduce several deleterious effects into fabrication/operational processes in comparison to conventional planar NAND string architectures having single crystalline silicon channels. For example, one operational challenge for a vertical NAND string relates to maintaining the boosted channel voltage on inhibited pillars during programming operations. Localized gap-state defects in the channel material, may introduce a rate-limiting channel-boost voltage-loss mechanism occurring at the edge of the string adjacent to select gate drain on program inhibited strings that potentially poses a serious limitation for achieving programming operational requirements of an array of vertical NAND strings. The voltage-loss mechanism may be unavoidable when using a non-crystalline channel material (i.e., polysilicon) under standard NAND operation conditions.
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